1. Field of the Invention
The present invention relates to synchronous semiconductor memory devices externally inputting/outputting a signal in synchronization with a clock signal which is externally applied periodically, and more particularly, to a synchronous dynamic random access memory (which is hereinafter referred to as an SDRAM) allowing random access.
2. Description of the Background Art
In a memory application system, although a dynamic random access memory (a DRAM) which is used as a main storage is increasingly becoming higher in speed, an operation speed thereof is not still following that of a micro processor unit (MPU). As a result, it is often said that the performance of the whole system is limited by the access and cycle time of the DRAM. Recently, a double data rate SDRAM (DDR SDRAM) has been proposed as a main storage for a high speed MPU which operates in synchronization with a complementary clock signal.
For allowing rapid access in the DDR SDRAM, a specification has been proposed which allows rapid access of for example four successive data for one data input/output terminal in synchronization with a complementary system clock signal (ext. CLK, ext. / CLK; / hereinafter represents inversion, designation, complementariness or the like).
FIG. 19 is a diagram of operation waveform showing an operation of the DDR SDRAM at the time of accessing.
In the DDR SDRAM, 8-bit data (byte data) can be input or output to or from data input/output terminals DQ0 to DQ7, and FIG. 19 shows an operation of successively writing or reading four data (8.times.4=32 bits in total).
The number of successively read data is called a burst length and can be changed by a mode register in the DDR SDRAM.
An operation mode is determined by a combination of states of external control signals /RAS, /CAS and /WE at the edge of an external clock signal ext. CLK. The combination of states of the external control signals is generally called a command. External control signals /RAS, /CAS and /WE respectively correspond to a row address strobe signal, a column address strobe signal and a write enable signal. A signal Add. is an address signal which is externally applied, a signal DQS is a data strobe signal indicating a timing of data inputting/outputting, and a signal D/Q is a data signal which is input/output through the data input/output terminal.
Referring to FIG. 19, at a time t1, external control signals /RAS, /CAS and /WE and address signal Add. are incorporated at the rising edge of clock signal ext. CLK. Address signal Add. is applied by time divisionally multiplexing row and column address signals X and Y. If external control signal /RAS is at "L" (LOW) level in an active state and the rising edge of clock signal ext. CLK at t1, address signal Add. at the time is incorporated as a row address Xa.
If external control signal /CAS is at the L level in the active state at the rising edge of clock signal ext. CLK at a time t2, address signal Add. at the time is incorporated as a column address Yb.
The signal representing the command and the address signal are incorporated at the rising edge of ext. CLK. An operation of selecting a row and column is performed in the DDR SDRAM in accordance with incorporated row column addresses Xa and Yb.
At a time t4, when a prescribed clock period (which is 3.5 clock cycles in FIG. 19) is elapsed after external control signal /RAS falls to the L level, the first four data q0, q1, q2 and q3 are output from time t4 to t8. The four data are output in response to a cross point of clock signals ext. CLK and ext. /CLK.
For enabling high speed data transfer, a data strobe signal DQS for transmitting a timing at which the data is received is also output in phase with the output data.
Further, at a time t3, rewriting (precharging) to a memory cell is performed if external control signals /RAS and /WE are at the L level at the rising edge of clock signal ext. CLK.
The writing operation is represented by waveforms after a time t9. In the writing operation, a row address Xc is incorporated as in the case of the reading of the data.
At a time t10, if external control signals /CAS and /WE are both at the L level in the active state at the rising edge of clock signal ext. CLK, column address Yd is incorporated and a data d0 which has been applied at a time t11 is also incorporated as the first data to be written.
In other words, a row and column selection operation is performed in the DDR SDRAM in response to the fall of external control signals /RAS and /CAS. Input data d1, d2 and d3 are sequentially incorporated in synchronization with data strobe signal DQS from time t12 to t14, and the input data are written to the memory cell.
As described above, in the conventional DRAM which does not operate in synchronization with the clock, the address signal, input data or the like are incorporated in synchronization with external control signals such as row address strobe signal /RAS and column address strobe signal /CAS for operation. In the SDRAM, however, external signals such as address strobe signals /RAS and /CAS and address signal Add. are incorporated at the rising edge of clock signal ext. CLK, and the input data is incorporated in synchronization with data strobe signal DQS.
Thus, one advantage of performing the synchronization operation for externally incorporating a signal and data in synchronization with the external clock signal is that it is necessary to keep a large margin of data input/output timing. It is because that the skew of the address signal (the difference in timing) does not affect the cycle time. As a result, cycle time can be reduced.
As an architecture for implementing the DDR SDRAM, C. Kim et al. have presented 2-bit prefetch mode (1998, IEEE International Solid State Circuits Conference pp.158-159).
FIG. 20 is a diagram schematically showing a structure of a DDR SDRAM having a 2-bit prefetch mode. FIG. 20 shows structures of a portion related to 1-bit data reading and of a peripheral circuit related to reading. The portion related to data reading is provided corresponding to each of data input/output terminals.
Referring to FIG. 20, the DDR SDRAM includes memory arrays 1aa, 1ab, 1ba and 1bb each having a plurality of memory cells arranged in a matrix.
The SDRAM has two banks, where memory arrays 1aa and 1ab form a bank A and memory arrays 1ba and 1bb form a bank B.
In banks A and B, memory arrays 1aa, 1ab, 1ba and 1bb respectively correspond to sub banks A0, A1, B0 and B1.
In the 2-bit prefetch mode, the SDRAM functions as a 2-bank SDRAM. Banks A and B can independently be driven into an active/inactive state. Designation of bank is performed by a bank address which is applied along with each command.
Provided for memory array 1aa are: a group of X decoders 2aa activated upon activation of a bank address signal BX for decoding row address signals X0-Xj (X0-j) and driving an addressed row of memory array 1aa into a selection state; a group of sense amplifiers 3aa activated upon activation of a sense amplifier activation signal .phi.SAA for detecting, amplifying and latching data for memory cell which is connected to a selected row of memory array laa; and a group Y decoders 4aa activated upon activation of a bank address signal BY for decoding column address signals YE0-YEk (YE0-k) and selecting an addressed column of memory array 1aa.
A memory cell in the column which is selected by a group of Y decoders 4aa is connected to an internal data bus 5aa. Bank address signal BX is applied along with an active command or a precharge command which instructs return to the precharged state. Bank address signal BY is applied along with a read command or write command.
Provided for memory array 1ab are: a group of X decoders 2ab activated upon activation of bank address signal BX for decoding row address signals X0-Xj (X0-j) and driving an addressed row of memory array 1ab into the selection state; a group of sense amplifier 3ab activated upon activation of sense amplifier activation signal .phi.SAA for detecting, amplifying and latching data for memory cell which is connected to a selected row of memory array 1ab; and a group of Y decoders 4ab activated upon activation of bank address signal BY for decoding column address signals YO0-YOk (YO0-k) and selecting an addressed column of memory array 1ab.
A memory cell in the column which is selected by a of group of Y decoders 4ab is connected to an internal data bus 5ab.
Provided for memory array 1ba are: a group of X decoders 2ba activated upon activation of a bank address signal /BX for decoding row address signals X0-Xj (X0-j) and driving an addressed row of memory array 1ba into the selection state; a group of sense amplifiers 3ba activated upon activation of a sense amplifier activation signal .phi.SAB for detecting, amplifying and latching data for memory cell which is connected to the selected row of memory array 1ba; and a group of Y decoders 4ba activated upon activation of a bank address signal /BY for decoding column address signals YE0-YEk (YE0-k) and selecting an addressed column of memory array 1ba.
A memory cell in the column which is selected by a group of Y decoders 4ba is connected to an internal data bus 5ba.
Provided for memory array 1bb are: a group of X decoders 2bb activated upon activation of bank address signal /BX for decoding row address signals X0-Xj (X0-j) and driving an addressed row of memory array 1bb into the selection state; a group of sense amplifiers 3bb activated upon activation of sense amplifier activation signal .phi.SAB for detecting, amplifying and latching data for memory cell which is connected to the selected row of memory array 1bb; and a group of Y decoders 4bb activated upon activation of bank address signal /BY for decoding column address signals YO0-YOk (YO0-k) for selecting an addressed column of memory array 1bb.
A memory cell in the column which is selected by a group of Y decoders 4bb is connected to an internal data bus 5bb.
Here, the group of X decoders includes X decoders arranged corresponding to rows, the group of sense amplifiers includes sense amplifiers arranged corresponding to the columns of a corresponding to memory array, and the group of Y decoders includes Y decoders arranged corresponding to columns.
In memory arrays 1aa and 1ab, memory selection operations are simultaneously performed in accordance with bank address signals BX and BY. On the other hand, in memory arrays 1ba and 1bb, selection operations are simultaneously performed in accordance with bank address signals /BX and /BY.
For reading data from memory array 1aa, a read preamplifier/register 22a is provided for receiving, amplifying and latching data from memory array 1aa which has been read onto internal data bus 5aa by a group of sense amplifiers 3aa in response to activation of a register activation signal .phi.RBA 0.
For reading data from memory array 1ab, a read preamplifier/register 22b is provided for receiving, amplifying and latching data from memory array 1ab which has been read onto internal data bus 5ab by a group of sense amplifiers 3ab in response to activation of a register activation signal .phi.RBA 1.
For reading data from memory array 1ba, a read preamplifier/register 24a is provided for receiving, amplifying and latching data from memory array 1ba which has been read onto internal data bus 5ba by a group of sense amplifiers 3ba in response to activation of a register activation signal .phi.RBB 0.
For reading data from memory array 1bb, a read preamplifier/register 24b is provided for receiving, amplifying and latching data from memory array 1bb which has been read onto internal data bus 5bb by a group of sense amplifiers 3bb in response to activation of a register activation signal .phi.RBB 1.
A bank selector 302a is provided for read preamplifier/registers 22a and 24a. Bank selector 302a selects and outputs one of a data signal /DAA0 output from read preamplifier/register 22a and a data signal /DAB0 output from read preamplifier/register 24a in accordance with data selection signals BA0, /BA0, BA1 and /BA1.
A bank selector 302b is provided for read preamplifier/registers 22b and 24b. Bank selector 302b selects and outputs one of a data signal /DAA1 output from read preamplifier/register 22b and a data signal /DAB1 output from read preamplifier/register 24b in accordance with data selection signals BA0, /BA0, BA1 and /BA1.
Provided for bank selectors 302a and 302b are: a prefetch selector 304 selecting a signal from one of bank selectors 302a and 302b in accordance with selection signals .phi.SEO and .phi.SEE; an output buffer 28 receiving and amplifying an output from prefetch selector 304; and a data input/output terminal 6 externally outputting an output signal from output buffer 28.
The synchronous semiconductor memory device further includes a control signal generation circuit 13 incorporating external control signals ext. /RAS, ext. /CAS, ext. /CS and ext. /WE which are respectively applied to input terminals 12a, 12b, 12c and 12d in synchronization with the rising of clock signal CLK and inverting the states thereof for producing internal control signals .phi.xa, .phi.ya, .phi.W, .phi.CS, .phi.R and .phi.CA.
Signal ext. /CS is a chip select signal, and the synchronous semiconductor memory device inputs/outputs data when chip select signal ext. /CS is in the activation state.
Clock signal CLK is internally generated in accordance with an external clock signal ext. CLK.
Signal .phi.xa is activated when the active command is applied and instructs incorporation of the row address signal. Signal .phi.ya is activated when the read or write command is applied and instructs incorporation of the column address signal. Signal .phi.W is activated when the write command is applied and instructs writing of data. Signal .phi.R is activated when the active command is applied and activates a circuit in the portion related to row selection. Signal .phi.CA is activated when the read or write command is applied and activates a circuit in the portion related to column selection and data inputting/outputting (a column related circuit).
The synchronous semiconductor memory device further includes: an X address buffer 14 incorporating external address signals ext. A0-Ai (A0-i) in response to activation of a row address incorporated instruction signal .phi.xa for generating internal row address signals X0-Xj (X0-j) and bank address signal BX; a Y address buffer 15 activated upon activation of a column address incorporation instruction signal .phi.ya for incorporating external address signals ext. A0-Ai and generating an internal column address signal; and a Y address operation circuit 16 changing an address in a prescribed sequence in synchronization with clock signal CLK using an internal column address signal which is applied from Y address buffer 15 as a leading address for generating even column address signals YE0-YEk (YE0-k), odd column address signals YO0-YOk (YO0-k) and bank address signals BY, BA0,BA1 (BAO, 1), /BA0, /BA1 (/BA0, 1).
Y address operation circuit 16 includes a burst address counter and changes the column address signal every two clock cycles.
The synchronous semiconductor memory device further includes: a clock counter 17 counting internal clock signal CLK in accordance with activation of column related activation signal .phi.CA for generating a count up signal at a prescribed timing in accordance with the count value; and a control signal generation circuit 32 receiving the count up signal from clock counter 17, bank address signals BX and BY and a least significant bit Y0 of the column address signal for producing various internal control signals .phi.RBB0, .phi.RBB1, .phi.RBA0, .phi.RBA1, .phi.SAA, .phi.SAB, .phi.SEO and .phi.SEE.
A control signal for a bank which is designated in accordance with bank address signals BX and BY is brought into an active state. The least significant bit of Y0 of the column address signal is used for indicating which one of the two memory arrays included in one bank should be first accessed.
Clock counter 17 counts a CAS latency and burst length, and generates a count up signal at a prescribed timing in accordance with a designated operation mode.
A circuit related to writing is not shown in FIG. 20.
The synchronous semiconductor memory device is characterized in that each bank is divided into two sub banks and, a read preamplifier, register or the like is provided corresponding to each sub bank. Therefore, the number of the read preamplifiers, registers or the like is twice that of a usual SDRAM. In FIG. 20, the synchronous semiconductor memory device is exemplified as having two banks. The banks can independently be accessed.
FIG. 21 is a circuit diagram showing an exemplary structure of bank selector 302a shown in FIG. 20.
Referring to FIG. 21, bank selector 302a includes: P channel MOS transistors 322 and 324 connected in series between a power supply node and a node N50 and respectively having their gates receiving a data signal /DAA0 and a data selection signal /BA0; N channel MOS transistors 326 and 328 connected in series between node N50 and a ground node and respectively having their gates receiving a data selection signal BA0 and a data signal /DAA0; P channel MOS transistors 330 and 332 connected in series between a power supply node and node N50 and respectively having their gates receiving a data signal /DAB0 and a data selection signal /BA1; and N channel MOS transistor 334 and 336 connected in series between node N50 and a ground node and respectively having their gates receiving a data selection signal BA1 and a data signal /DAB0.
Node N50 is an output node of bank selector 302a, from which a data signal DATAE which is read from the memory array corresponding to an even address is output.
Bank selector 302a inverts data signal /DAA0 which has been read to and latched at a read preamplifier/register 22a from memory array 1aa and output it as data signal DATAE when data selection signal BA0 is activated. On the other hand, when data selection signal BA1 is activated, bank selector 302a inverts data signal /DAB0 which is read to from memory array 1ba and latched at a read preamplifier/register 24a and outputs it as data signal DATAE.
FIG. 22 is a circuit diagram showing an exemplary structure of bank selector 302b shown in FIG. 20.
Referring to FIG. 22, bank selector 302b includes: P channel MOS transistors 342 and 344 connected in series between a power supply node and a node N52 and respectively having their gates receiving a data signal /DAA1 and data selection signal /BA0; N channel MOS transistors 346 and 348 connected in series between node N52 and a ground node and respectively having their gates receiving data selection signal BA0 and a data signal /DAA1; P channel MOS transistors 350 and 352 connected in series between the power supply node and node N52 and respectively having their gates receiving a data signal /DAB1 and data selection signal /BA1; and N channel MOS transistors 354 and 356 connected in series between node N 52 and a ground node and respectively having their gates receiving data selection signal BA1 and data signal /DAB1.
Node N52 is an output node of bank selector 302b, from which a data signal DATA0 which is read from the memory array corresponding to an odd address is output.
When data selection signal BA1 is activated, bank selector 302b inverts data signal /DAA1 which is read to and latched at a read preamplifier/register 22b from memory array 1ab and outputs it as data signal DATA0. When data selection signal BA1 is activated, on the other hand, bank selector 302b inverts data signal /DAB1 which is read to and latched at a read preamplifier/register 24b from memory array 1bb and outputs it as data signal DATAO.
FIG. 23 a circuit diagram showing an exemplary structure of prefetch selector 304 shown in FIG. 20.
Referring to FIG. 23, prefetch selector 304 includes: an inverter 362 receiving and inverting data signal DATAE for outputting it to a node N54 when a control signal SEE is activated; and an inverter 364 receiving and inverting data signal DATAO for outputting it to node N54 when a control signal SEO is activated. Node N54 is an output node of prefetch selector 304 and outputs a data signal to output buffer 28.
Referring to FIG. 20 again, to briefly describe the operation, when a read command is input from terminals 12a to 12d, a Y decoder corresponding to an address thereof is activated. At the time, a selection line corresponding to the applied address and an address which is obtained by incrementing the address by one are activated. Thus, 2-bit data are read to read preamplifiers 22a, 22b, 24a, and 24b for each DQ terminal, and data of the bank which is selected by bank selectors 302a and 302b are input to the prefetch selector. The input 2-bit data are alternately output to the output buffer by the prefetch selector. This architecture advantageously reduces an operation frequency of the memory array to half as compared with the reading frequency, thereby facilitating the array operation.
In the DDR SDRAM, data is output using a cross point of clock signal ext. CLK as a trigger. A data rate which is twice a single data rate of the SDRAM which outputs data in synchronization with the rising edge of clock signal ext. CLK is achieved. Thus, when it is operated with a low speed tester having a low clock frequency, the operation frequency of the DDR SDRAM must be reduced for data determination. This results in a longer test time and increase in manufacturing cost of the synchronous semiconductor memory device.
However, the operation frequency of the externally output data is twice that of the memory array, that is, the externally output data is high in the operation frequency, and therefore the inspection of the synchronous semiconductor memory device requires an expensive tester which can operate at a high speed and is not possible with an inexpensive tester which is low in operation frequency.